"Cell" is a term used in the art to describe a circuit configuration which is self-contained and fixed in design. The term cell should be understood as defining a sub-circuit which is densely packed and which therefore does not provide for conductive lines to pass through the circuit or provides only very limited line-pass-through capability. These sub-circuits range from simple AND or OR logic circuits and the like to considerably larger groupings.
"Macro" is a term recently becoming used in the art to describe cells of particularly large and generally sophisticated sub-circuits. A macro may be relatively small, such as a data serializer-deserializer, or may be very large such as a memory bank having thousands of memory sites. Each such sub-circuit is a macro when its design is physically so compact as to not provide for conductive lines from another sub-circuit to pass through the circuit, or to provide only a very limited path for crossing conductive lines.
Macro circuits, of course, do provide terminals, generally at their periphery, to receive conductive lines from other circuits. These conductive lines integrate the macro with other circuitry on the substrate. Operatively interconnected macros on the same semiconductor substrate constitute a completed "chip."
Macros are now standard in the art and are of great economic significance since they constitute optimized, efficient designs of functional elements which may be readily combined without change with other macros to make sophisticated devices. Great attention and effort can be applied to perfect the design of each macro, with emphasis on packing the circuit elements together as densely as possible. This design may be used in any number of different chips and may be reproduced by standard integrated-circuit-fabrication techniques. The design may be efficiently replicated perhaps thousands of times on a single chip.
Cells must be separated on the chip so as to leave space for lines interconnecting the cells. The conventional configuration of cells on the chip is an ordered pattern leaving columns in which interconnecting lines may be positioned. Where all cells are substantially the same size, that interconnecting configuration may be relatively efficient.
"Master slice" or "gate array" is commonly used alternative technology for a configuration of columns of cells of all the same size. "Master image" is commonly used terminology for a configuration of cells similar to master slice except the cells vary in height and the columns vary in width, although each column is assigned a uniform width. Because of the constraints on the width of the columns, the master slice and master image cells typically are relatively small sub-circuits such as AND and OR logic blocks. No conductive pass through is typically provided since the cell boundaries are contiguous and cross paths are not provided within the cells. Although this invention has major utility where the cells are macros, typical master slice and master image configurations can employ this invention to advantage.
The fabrication of integrated circuits on a substrate involves the treatment of a starting substrate by different steps at different levels. These levels are physically spaced from one another and are generally parallel, although not strictly so. Accordingly, the levels do not necessarily interconnect electrically and levels which are to be connected electrically are typically interconnected using a via, which is a connective path perpendicular to the two levels being connected. Such fabrication techniques are entirely standard and state-of-the-art. This invention employs such state-of-the-art fabrication in patterns as will be described to achieve interconnection of the cells.
As will be immediately understood by those familiar with the integrated circuit fabrication art, the number of levels and the type of activation at each level to achieve conductivity or to achieve a transistor barrier or to fabricate a transistor is a matter of initial design choice which may vary greatly. Similarly, the number of levels is a matter of choice and depends upon the initial choice of the circuit designer. A large investment in capital equipment is effected to manufacture large numbers of integrated circuits employing the technology selected. Accordingly, after the initial selection of technology, including the number of levels and the type of treatment at different levels, the technology selected will constitute a constraint which must be followed in order to achieve mass production using the equipment assembled to carry out the mass production.
This invention is not limited by the type of technology involved, although where the interconnection of cells is concerned, it is directed to that technology which has two conductive levels. Typically the conductive material is metal. A conductive level in such technology is a level at which the processing step includes the capability of applying metal or the essential equivalent as highly conductive lines from one point to another on the circuit substrate. These conductive lines are the interconnections between cells, equivalent to wires connecting resistors, transistors, vacuum tubes and reactive impedances and other elements in large-scale, non-integrated circuits, Normally, the cells will occupy one of the two metal levels along with whatever metal lines are applied to that metal level. This avoids the necessity for a via to reach each macro from a metal level. The second metal level will physically clear the cells and, of course, the metal on the first metal level. (Typically, the technology will include a polysilicon level, which is used for certain connections, but is electrically inferior to the metal levels and therefore not used for long interconnections of cells.)